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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adsp-2184 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 dsp microcomputer functional block diagram features performance 25 ns instruction cycle time 40 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 200 cycle recovery from power-down condition low power dissipation in idle mode integration adsp-2100 family code compatible, with instruction set extensions 20k bytes of on-chip ram, configured as 4k words on-chip program memory ram and 4k words on-chip data memory ram dual purpose program memory for both instruction and data storage independent alu, multiplier/accumulator and barrel shifter computational units two independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution programmable 16-bit interval timer with prescaler 100-lead lqfp system interface 16-bit internal dma port for high speed access to on-chip memory (mode selectable) 4 mbyte byte memory interface for storage of data tables and program overlays (made selectable) 8-bit dma to byte memory for transparent program and data memory transfers (mode selectable) i/o memory interface with 2048 locations supports parallel peripherals (mode selectable) programmable memory strobe and separate i/o memory space permits glueless system design (mode selectable) programmable wait state generation two double-buffered serial ports with companding hardware and automatic data buffering automatic booting of on-chip program memory from byte-wide external memory, e.g., eprom, or through internal dma port six external interrupts 13 programmable flag pins provide flexible system signaling uart emulation through software sport reconfiguration ice-port? emulator interface supports debugging in final systems general description the adsp-2184 is a single-chip microcomputer optimized for digital signal processing (dsp) and other high speed numeric processing applications. the adsp-2184 combines the adsp-2100 family base archi- tecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities and on-chip program and data memory. the adsp-2184 integrates 20k bytes of on-chip memory con- figured as 4k words (24-bit) of program ram and 4k words (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment. the adsp-2184 is available in 100-lead lqfp package. in addition, the adsp-2184 supports instructions that include bit manipulationsbit set, bit clear, bit toggle, bit test alu constants, multiplication instruction (x squared), biased round- ing, result free alu operations, i/o memory transfers, and global interrupt masking for increased flexibility. fabricated in a high speed, double metal, low power, cmos process, the adsp-2184 operates with a 25 ns instruction cycle time. every instruction can execute in a single processor cycle. ice-port is a trademark of analog devices, inc. all trademarks are the property of their respective holders. serial ports sport 1 sport 0 memory programmable i/o and flags byte dma controller 4k 3 24 program memory 4k 3 16 data memory timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data external data bus external address bus internal dma port external data bus or full memory mode host mode
adsp-2184 C2C rev. 0 the adsp-21xx family dsps contain a shadow bank register that is useful for single cycle context switching of the processor. the adsp-2184s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. in one processor cycle the adsp-2184 can: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation this takes place while the processor continues to: ? receive and transmit data through the two serial ports ? receive or transmit data through the internal dma port ? receive or transmit data through the byte dma port ? decrement timer development system the adsp-2100 family development software, a complete set of tools for software and hardware system development, sup- ports the adsp-2184. the system builder provides a high level method for defining the architecture of systems under develop- ment. the assembler has an algebraic syntax that is easy to program and debug. the linker combines object files into an executable file. the simulator provides an interactive instruction- level simulation with a reconfigurable user interface to display different portions of the hardware environment. a prom splitter generates prom programmer compatible files. the c compiler, based on the free software foundations gnu c compiler, generates adsp-2184 assembly source code. the source code debugger allows programs to be corrected in the c environment. the runtime library includes over 100 ansi-standard mathematical and dsp-specific functions. the ez-kit lite is a hardware/software kit offering a complete development environment for the entire adsp-21xx family: an adsp-218x based evaluation board with pc monitor software plus assembler, linker, simulator and prom splitter software. the adsp-21xx ez-kit lite is a low cost, easy to use hardware platform on which you can quickly get started with your dsp soft- ware de sign. the ez-kit lite includes the following features: ? 33 mhz adsp-2181 ? full 16-bit stereo audio i/o with ad1847 soundport ? codec ? rs-232 interface to pc with microsoft windows ? 3.1 control software ? ez-ice ? connector for emulator control ? dsp demo programs the adsp-218x ez-ice emulator aids in the hardware debug- ging of an adsp-2184 system. the emulator consists of hard- ware, host computer resident software, and the target board connector. the adsp-2184 integrates on-chip emulation sup- port with a 14-pin ice-port interface. this interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other adsp-2100 family ez- ices. the adsp-2184 device need not be removed from the target system when using the ez-ice, nor are any adapters needed. due to the small footprint of the ez-ice connector, emulation can be supported in final board designs. the ez-ice performs a full range of functions, including: ? in-target operation ? up to 20 breakpoints ? single-step or full-speed operation ? registers and memory values can be examined and altered ? pc upload and download functions ? instruction-level emulation of program booting and execution ? complete assembly and disassembly of instructions ? c source-level debugging see designing an ez-ice-compatible target system in the adsp-2100 family ez-tools manual (adsp-2181 sections), as well as the target board connector for ez-ice probe section of this data sheet, for the exact specifications of the ez-ice target board connector. additional information this data sheet provides a general overview of adsp-2184 functionality. for additional information on the architecture and instruction set of the processor, refer to the adsp-2100 family users manual, third edition . for more information about the development tools, refer to the adsp-2100 family development tools data sheet . architecture overview the adsp-2184 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single pro- cessor cycle. the adsp-2184 assembly language uses an alge- braic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports sport 1 sport 0 memory programmable i/o and flags byte dma controller 4k 3 24 program memory 4k 3 16 data memory timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data external data bus external address bus internal dma port external data bus or full memory mode host mode figure 1. block diagram figure 1 is an overall block diagram of the adsp-2184. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provi- sions to support multiprecision computations. the alu per- forms a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arith- metic shifts, normalization, denormalization and derive expo- nent operations. the shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. soundport and ez-ice are registered trademarks of analog devices, inc. windows is a registered trademark of microsoft corporation.
adsp-2184 C3C rev. 0 the internal result (r) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. with internal loop counters and loop stacks, the adsp-2184 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches from data memory and pro- gram memory. each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four pos- sible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the adsp-2184 to fetch two operands in a single cycle, one from program memory and one from data memory. the adsp- 2184 can fetch an operand from program memory and the next instruction in the same cycle. when configured in host mode, the adsp-2184 has a 16-bit internal dma port (idma port) for connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsps on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with programmable wait state generation. external devices can gain control of external buses with bus request/grant signals ( br , bgh and bg ). one execution mode (go mode) allows the ad sp-2184 to continue running from on-chip memory. normal execution mode requires the processor to halt while buses are granted. the adsp-2184 can respond to eleven interrupts. there are up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the adsp-2184 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the adsp-2184 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the adsp-2184 sports. for additional information on serial ports, refer to the adsp- 2100 family users manual, third edition . ? sports are bidirectional and have a separate, double-buff- ered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m -law companding according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed, serial bitstream. ? sport1 can be configured to have two external interrupts ( irq0 and irq1 ) and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. pin descriptions the adsp-2184 is available in a 100-lead lqfp package. in order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, inter- rupt and external bus pins have dual, multiplexed functionality. the external bus pins are configured during reset only, while serial port pins are software configurable during program execu- tion. flag and interrupt functionality is retained concurrently on multiplexed pins. in cases where pin functionality is re- configurable, the default state is shown in plain text; alternate functionality is shown in italics.
adsp-2184 C4C rev. 0 common-mode pins # input/ pin of out- name(s) pins put function reset 1 i processor reset input br 1 i bus request input bg 1 o bus grant output bgh 1 o bus grant hung output dms 1 o data memory select output pms 1 o program memory select output ioms 1 o i/o memory select output bms 1 o byte memory select output cms 1 o combined memory select output rd 1 o memory read enable output wr 1 o memory write enable output irq2/ 1 i edge- or level-sensitive interrupt request 1 pf7 i/o programmable i/o pin irql0/ 1 i level-sensitive interrupt requests 1 pf5 i/o programmable i/o pin irql1/ 1 i level-sensitive interrupt requests 1 pf6 i/o programmable i/o pin irqe/ 1 i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin pf3 1 i/o programmable i/o pin mode c/ 1 i mode select inputchecked only during reset pf2 i/o programmable i/o pin during normal operation mode b/ 1 i mode select inputchecked only during reset pf1 i/o programmable i/o pin during normal operation mode a/ 1 i mode select inputchecked only during reset pf0 i/o programmable i/o pin during normal operation clkin, xtal 2 i clock or quartz crystal input clkout 1 o processor clock output sport0 5 i/o serial port i/o pins sport1/ 5 i/o serial port i/o pins irq1:0 edge- or level-sensitive i nterrupts, fi, fo flag in, flag out 2 pwd 1 i power-down control input pwdack 1 o power-down control output fl0, fl1, fl2 3 o output flags v dd and gnd 16 i power and ground ez-port 9 i/o for emulation use notes 1 interrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, the dsp will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2 sport configuration determined by the dsp system control register. soft- ware configurable. memory interface pins the adsp-2184 processor can be used in one of two modes: full memory mode, which allows bdma operation with full external overlay memory and i/o capability, or host mode, which allows idma operation with limited external addressing capabilities. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the processor is running. full memory mode pins (mode c = 0) # of input/ pin name pins output function a13:0 14 o address output pins for pro- gram, data, byte and i/o spaces d23:0 24 i/o data i/o pins for program, data, byte and i/o spaces (8 msbs are also used as byte memory addresses) host mode pins (mode c = 1) # of input/ pin name pins output function iad15:0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, program, data, or byte access d23:8 16 i/o data i/o pins for program, data byte and i/o spaces iwr 1 i idma write enable ird 1 i idma read enable ial 1 i idma address latch pin is 1 i idma select iack 1 o idma port acknowledge in host mode, external peripheral addresses can be decoded using the a0, bms , cms , pms , dms , and ioms signals. setting memory mode memory mode selection for the adsp-2184 is made during chip reset through the use of the mode c pin. this pin is multi- plexed with the dsps pf2 pin, so care must be taken in how the mode selection is made. the two methods for selecting the value of mode c are passive and active. passive configuration involves the use a pull-up or pull-down resistor connected to the mode c pin. to minimize power consumption, or if the pf2 pin is to be used as an output in the dsp application, a weak pull-up or pull-down, on the order of 100 k w , can be used. this value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processors output driver. for minimum power consumption during power-down, reconfigure pf2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. active configuration involves the use of a three-stateable exter- nal driver connected to the mode c pin. a drivers output en- able should be connected to the dsps reset signal such that it only drives the pf2 pin when reset is active (low). after reset is deasserted, the driver should three-state, thus allow- ing full use of the pf2 pin as either an input or output.
adsp-2184 C5C rev. 0 to minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. this ensures that the pin will be held at a constant level and not oscillate should the three-state drivers level hover around the logic switching point. interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. the adsp-2184 provides four dedicated external interrupt input pins, irq2 , irql0 , irql1 and irqe (shared with the pf7:4 pins). in addition, sport1 may be reconfigured for irq0 , irq1 , flag_in and flag_out, for a total of six external interrupts. the adsp-2184 also supports internal interrupts from the timer, the byte dma port, the two serial ports, software and the power-down control circuit. the inter- rupt levels are internally prioritized and individually maskable (except power-down and reset ). the irq2 , irq0 and irq1 input pins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level-sensitive and irqe is edge-sensitive. the priorities and vector addresses of all interrupts are shown in table i. table i. interrupt priority & interrupt vector addresses source of interrupt interrupt vector address (hex) reset (or power-up with pucr = 1) 0000 (highest priority) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 (lowest priority) interrupt routines can either be nested, with higher priority interrupts taking precedence, or processed sequentially. inter- rupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the power-down interrupt is nonmaskable. the adsp-2184 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect serial port autobuffering or dma transfers. the interrupt control register, icntl, controls interrupt nest- ing and defines the irq0 , irq1 and irq2 external interrupts to be either edge- or level-sensitive. the irqe pin is an external edge-sensitive interrupt and can be forced and cleared. the irql0 and irql1 pins are external level-sensitive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preserve the processor status and are automati- cally maintained during interrupt handling. the stacks are twelve levels deep to allow interrupt, loop and subroutine nesting. the following instructions allow global enable or disable servic- ing of the interrupts (including power-down), regardless of the state of imask. disabling the interrupts does not affect serial port autobuffering or dma. ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the adsp-2184 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. these modes are: ? power-down ? idle ? slow idle the clkout pin may also be disabled to reduce external power dissipation. power-down the adsp-2184 processor has a low power feature that lets the processor enter a very low power dormant state through hard- ware or software control. following is a brief list of power-down features. refer to the adsp-2100 family users manual, third edition , system interface chapter, for detailed information about the power-down feature. ? quick recovery from power-down. the processor begins executing instructions in as few as 200 clkin cycles. ? support for an externally generated ttl or cmos proces- sor clock. the external clock can continue running during power-down without affecting the lowest power rating and 200 clkin cycle recovery. ? support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approxi- mately 4096 clkin cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 clkin cycle start-up. ? power-down is initiated by either the power-down pin ( pwd ) or the software power-down force bit. ? interrupt support allows an unlimited number of instructions to be executed before optionally powering down. the power- down interrupt also can be used as a nonmaskable, edge- sensitive interrupt. ? context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. ? the reset pin also can be used to terminate power-down. ? power-down acknowledge pin indicates when the processor has entered power-down.
adsp-2184 C6C rev. 0 idle when the adsp-2184 is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruction. in idle mode idma, bdma and autobuffer cycle steals still occur. slow idle the idle instruction is enhanced on the adsp-2184 to let the processors internal clock signal be slowed, further reducing power consumption. the reduced clock frequency, a program- mable fraction of the normal clock rate, is specified by a select- able divisor given in the idle instruction. the format of the instruction is idle (n); where n = 16, 32, 64 or 128. this instruction keeps the proces- sor fully functional, but operating at the slower clock rate. while it is in this state, the processors other internal clock signals, such as sclk, clkout and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle (n) instruction is used, it effectively slows down the processors internal clock and thus its response time to in- coming interrupts. the one-cycle response time of the standard idle state is increased by n , the clock divisor. when an enabled interrupt is received, the adsp-2184 will remain in the idle state for up to a maximum of n processor cycles ( n = 16, 32, 64 or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 2 shows typical basic system configurations with the adsp-2184, two serial devices, a byte-wide eprom and optional external program and data overlay memories (mode sel ectable). programmable wait state generation allows the processor to connect easily to slow peripheral devices. the adsp-2184 also provides four external interrupts and two serial ports or six external interrupts and one serial port. host memory mode allows access to the full external data bus, but limits addressing to a single address bit (a0). additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals. 1/2x clock or crystal serial device serial device sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 a0-a21 data cs byte memory i/o space (peripherals) cs data addr data addr 2048 locations overlay memory two 8k pm segments two 8k dm segments d 23-0 a 13-0 d 23-8 a 10-0 d 15-8 d 23-16 a 13-0 14 24 fl0-2 pf3 clkin xtal addr13-0 data23-0 bms ioms pms dms cms br bg bgh pwd adsp-2184 1/2x clock or crystal serial device serial device system interface or m controller 16 1 16 sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 ird /d6 iwr /d7 is /d4 ial/d5 iack /d3 iad15-0 idma port fl0-2 pf3 clkin xtal addr0 data23-8 bms ioms pms dms cms br bg bgh pwd adsp-2184 irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf1 mode a/pf0 host memory mode irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf1 mode a/pf0 full memory mode pwdack pwdack cs figure 2. basic system configuration
adsp-2184 C7C rev. 0 clock signals the adsp-2184 can be clocked by either a crystal or a ttl- compatible clock signal. the clkin input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. the only exception is while the processor is in the power- down state. for additional information, refer to chapter 9, adsp-2100 family users manual , third edition , for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is con- nected to the processors clkin input. when an external clock is used, the xtal input must be left unconnected. the adsp-2184 uses an input clock with a frequency equal to half the instruction rate; a 20.00 mhz input clock yields a 25 ns processor cycle (which is equivalent to 40 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the adsp-2184 includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be con- nected across the clkin and xtal pins, with two capacitors connected as shown in figure 3. capacitor values are dependent on crystal type and should be specified by the crystal manufac- turer. a parallel-resonant, fundamental frequency, microproces- sor-grade crystal should be used. a clock output (clkout) signal is generated by the proces- sor at the processors cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control register. clkin clkout xtal dsp figure 3. external crystal connections reset the reset signal initiates a master reset of the adsp-2184. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked, but does not include the crystal oscillator start-up time. during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the mini- mum pulsewidth specification, t rsp . the reset input contains some hysteresis; however, if you use an rc circuit is used to generate your reset signal, the use of an external schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. the first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. in an ez-ice-compatible system reset and ereset have the same functionality. for complete informa- tion, see designing an ez-ice-compatible systems section. memory architecture the adsp-2184 provides a variety of memory and peripheral interface options. the key functional groups are program memory, data memory, byte memory and i/o. program memory (full memory mode) is a 24-bit-wide space for storing both instruction opcodes and data. the adsp-2184 has 4k words of program memory ram on chip, and the capabil- ity of accessing up to two 8k external memory overlay spaces using the external data bus. both an instruction opcode and a data value can be read from on-chip program memory in a single cycle. data memory (full memory mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. the adsp-2184 has 4k words on data memory ram on chip. support also exists for up to two 8k external memory overlay spaces through the external data bus. byte memory (full memory mode) provides access to an 8-bit wide memory space through the byte dma (bdma) port. the byte memory interface provides access to 4 mbytes of memory by utilizing eight data lines as additional address lines. this gives the bdma port an effective 22-bit address range. on power-up, the dsp can automatically load bootstrap code from byte memory. i/o space (full memory mode) allows access to 2048 loca- tions of 16-bit-wide data. it is intended to be used to communi- cate with parallel peripheral devices such as data converters and external registers or latches. program memory the adsp-2184 contains 4k 24 of on-chip program ram. the on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. in addition, the adsp-2184 allows the use of 8k external memory overlays. the program memory space organization is controlled by the mode b pin and the pmovlay register. normally, the adsp- 2184 is configured with mode b = 0 and program memory organized as shown in figure 4. external 8k (pmovlay = 1 or 2, mode b = 0) 0x3fff 0x2000 0x1fff 4k internal 0x0000 program memory address 0x1000 0x0fff reserved memory range figure 4. program memory (mode b = 0)
adsp-2184 C8C rev. 0 when pmovlay is set to 1 or 2, external accesses occur at addresses 0x2000 through 0x3fff. the external address is generated as shown in table ii. table ii. pmovlay memory a13 a12:0 0 internal not applicable not applicable 1 external 13 lsbs of address overlay 1 0 between 0x2000 and 0x3fff 2 external 13 lsbs of address overlay 2 1 between 0x2000 and 0x3fff note: addresses 0x2000 through 0x3fff should not be accessed when pmovlay = 0. this organization provides for two external 8k overlay segments using only the normal 14 address bits, which allows for simple program overlays using one of the two external segments in place of the on-chip memory. care must be taken in using this overlay space in that the processor core (i.e., the sequencer) does not take into account the pmovlay register value. for example, if a loop operation is occurring on one of the external overlays and the program changes to another external overlay or internal memory, an incorrect loop operation could occur. in addition, care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack. when mode b = 1, booting is disabled and overlay memory is disabled the 4k internal pm cannot be accessed with mode b = 1. figure 5 shows the memory map in this configuration. reserved 0x3fff 0x2000 0x1fff 8k external 0x0000 program memory address figure 5. program memory (mode b = 1) data memory the adsp-2184 has 4k 16-bit words of internal data memory. in addition, the adsp-2184 allows the use of 8k external memory overlays. figure 6 shows the organization of the data memory. external 8k (dmovlay = 1, 2) internal 4k words data memory address 32 memoryC mapped registers 0x3fff 0x3feo 0x2fff 0x2000 0x1fff 0x0000 4064 reserved words 0x3fdf 0x3000 figure 6. data memory there are 4k words of memory accessible internally when the dmovlay register is set to 0. when dmovlay is set to 1 or 2, external accesses occur at addresses 0x0000 through 0x1fff. the external address is generated as shown in table iii. table iii. dmovlay memory a13 a12:0 0 internal not applicable not applicable 1 external 13 lsbs of address overlay 1 0 between 0x0000 and 0x1fff 2 external 13 lsbs of address overlay 2 1 between 0x0000 and 0x1fff this organization allows for two external 8k overlays using only the normal 14 address bits. all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register. i/o space (full memory mode) the adsp-2184 supports an additional external memory space called i/o space. this space is designed to support simple con- nections to peripherals or to bus interface asic data registers. i/o space supports 2048 locations. the lower eleven bits of the external address bus are used; the upper three bits are unde- fined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated three-bit wait state registers, iowait0-3, that specify up to seven wait states to be automatically generated for each of four regions. the wait states act on address ranges as shown in table iv. table iv. address range wait state register 0x000C0x1ff iowait0 0x200C0x3ff iowait1 0x400C0x5ff iowait2 0x600C0x7ff iowait3 composite memory select ( cms ) the adsp-2184 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. the cms signal is generated to have the same timing as each of the individual memory select signals ( pms , dms , bms , ioms ), but can combine their functionality. each bit in the cmssel register, when set, causes the cms signal to be asserted when the selected memory select is as- serted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of the memory and use either dms or pms as the additional address bit. the cms pin functions as the other memory select signals, with the same timing and bus request logic. a 1 in the enable bit causes the assertion of the cms signal at the same time as the selected memory select signal. all enable bits, except the bms bit, default to 1 at reset.
adsp-2184 C9C rev. 0 byte memory the byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. byte memory is accessed using the bdma feature. the byte memory space consists of 256 pages, each of which is 16k 8. the byte memory space on the adsp-2184 supports read and write operations as well as four different data formats. the byte memory uses data bits 15:8 for data. the byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. this allows up to a 4 meg 8 (32 megabit) rom or ram to be used without glue logic. all byte memory accesses are timed by the bmwait register. byte memory dma (bdma, full memory mode) the byte memory dma controller allows loading and storing of program instructions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processor is operating normally and steals only one dsp cycle per 8-, 16- or 24-bit word transferred. the bdma circuit supports four different data formats that are selected by the btype register field. the appropriate number of 8-bit accesses is done from the byte memory space to build the word size selected. table v shows the data formats sup- ported by the bdma circuit. table v. internal btype memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs unused bits in the 8-bit data memory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starting address for the external byte memory space. the 8-bit bmpage register specifies the starting page for the external byte memory space. the bdir register field selects the direction of the transfer. the 14-bit bwcount register specifies the number of dsp words to transfer and initiates the bdma circuit transfers. bdma accesses can cross page boundaries during sequential addressing. a bdma interrupt is generated on the completion of the number of transfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is gener- ated. the bmpage and bead registers must not be accessed by the dsp during bdma operations. the source or destination of a bdma transfer will always be on-chip program or data memory, regardless of the values of mode b, pmovlay or dmovlay. when the bwcount register is written with a nonzero value, the bdma circuit starts executing byte memory accesses with wait states set by bmwait. these accesses continue until the count reaches zero. when enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. the transfer takes one dsp cycle. dsp accesses to external memory have priority over bdma byte memory accesses. the bdma context reset bit (bcr) controls whether the processor is held off while the bdma accesses are occurring. setting the bcr bit to 0 allows the processor to continue opera- tions. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesses are occurring, to clear the context of the processor and start execution at address 0 when the bdma accesses have completed. internal memory dma port (idma port; host memory mode) the idma port provides an efficient means of communication between a host system and the adsp-2184. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word overhead. the idma port cannot, however, be used to write to the dsps memory- mapped control registers. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is com- pletely asynchronous and can be written to while the adsp- 2184 is operating at full speed. the dsp memory address is latched and then automatically incremented after each idma transaction. an external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this in- creases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle. when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location, the destination type specifies whether it is a dm or pm access. the falling edge of the idma address latch signal ( ial ) or the missing edge of the idma select signal ( is ) latches this value into the idmaa register. once the address is stored, data can then either be read from or written to the adsp-2184s on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the adsp-2184 that a particular transaction is required. in either case, there is a one-processor- cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is automati- cally incremented and another access can occur. through the idmaa register, the dsp can also specify the starting address and data format for dma operation.
adsp-2184 C10C rev. 0 bootstrap loading (booting) the adsp-2184 has two mechanisms to allow automatic load- ing of the internal program memory after reset. the method for booting is controlled by the mode a, b and c configuration bits as shown in table vi. these four states can be compressed into two-state bits by allowing an idma boot with mode c = 1. however, three bits are used to ensure future compatibility with parts containing internal program memory rom. bdma booting when the mode pins specify bdma booting, the adsp-2184 initiates a bdma boot sequence when reset is released. table vi. boot summary table mode c mode b mode a booting method 0 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is config- ured in full memory mode. 0 1 0 no automatic boot operations occur. program execution starts at external memory location 0. chip is configured in full memory mode. bdma can still be used but the pro- cessor does not automatically use or wait for these operations. 1 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is config- ured in host mode. additional interface hardware is required. 1 0 1 idma feature is used to load any internal memory as de- sired. program execution is held off until internal program memory location 0 is written to. chip is configured in host mode. the bdma interface is set up during reset to the following de- faults w hen bdma booting is specified: the bdir, bmpage, biad and bead registers are set to 0; the btype register is set to 0 to specify program memory 24-bit words; and the bwcount register is set to 32. this causes 32 words of on- chip program memory to be loaded from byte memory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes pro- gram execution to be held off until all 32 words are loaded into on-chip program memory. execution then begins at address 0. the idle instruction can also be used to allow the processor to hold off execution while booting continues through the bdma interface. for bdma accesses while in host mode, the ad- dresses to boot memory must be constructed externally to the adsp-2184. the only memory address bit provided by the processor is a0. idma port booting the adsp-2184 can also boot programs through its internal dma port. if mode c = 1, mode b = 0, and mode a = 1, the adsp-2184 boots from the idma port. the idma feature can load as much on-chip memory as desired. program execution is held off until on-chip program memory location 0 is written to. bus request and bus grant the adsp-2184 can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request ( br ) signal. if the adsp-2184 is not performing an external memory access, it responds to the active br input in the following processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , wr output drivers, ? asserting the bus grant ( bg ) signal, and ? halting program execution. if go mode is enabled, the adsp-2184 will not halt program execution until it encounters an instruction that requires an external memory access. if the adsp-2184 is performing an external memory access when the external device asserts the br signal, it will not three- state the memory interfaces or assert the bg signal until the processor cycle after the access completes. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, reenables the output drivers and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the adsp-2184 is ready to execute an instruction but is stopped because the external bus is already granted to another device. the other device can release the bus by deasserting bus request. once the bus is released, the adsp-2184 deasserts bg and bgh and executes the external memory access. flag i/o pins the adsp-2184 has eight general purpose programmable input/ output flag pins. they are controlled by two memory mapped registers. the pftype register determines the direction, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the adsp-2184s clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset.
adsp-2184 C11C rev. 0 in addition to the programmable flags, the adsp-2184 has five fixed-mode flags, flag_in, flag_out, fl0, fl1 and fl2. fl0-fl2 are dedicated output flags. flag_in and flag_out are available as an alternate configuration of sport1. note: pins pf0, pf1 and pf2 are also used for device configu- ration during reset. instruction set description the adsp-2184 assembly language instruction set has an alge- braic syntax that was designed for ease of coding and readabil- ity. the assembly language, which takes full advantage of the processors unique architecture, offers the following benefits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relo- cated to utilize on-chip memory and conform to the adsp- 2184s interrupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. designing an ez-ice-compatible system the adsp-2184 has on-chip emulation support and an ice-port, a special set of pins that interface to the ez-ice. t hese features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ices in-circuit probe, a 14-pin plug. issuing the chip reset command during emulation causes the dsp to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. if using a passive method of maintaining mode information (as discussed in setting memory modes), it does not matter that the mode information is latched by an emulator reset. however, if using the reset pin as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. one method of ensuring that the values located on the mode pins is the one that is desired to construct a circuit like the one shown in figure 7. this circuit will force the value located on the mode a pin to logic low, regardless if it latched via the reset or ereset pin. programmable i/o mode a/pfo reset ereset 1k v adsp-2184 figure 7. see the adsp-2100 family ez-tools data sheet for complete information on ice products. the ice-port interface consists of the following adsp-2184 pins: ebr ebg ereset ems eint eclk elin elout ee these adsp-2184 pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull-down resistors. the traces for these signals between the adsp-2184 and the connector must be kept as short as pos- sible, no longer than three inches. the following pins are also used by the ez-ice: br bg reset gnd the ez-ice uses the ee (emulator enable) signal to take con- trol of the adsp-2184 in the target system. this causes the processor to use its ereset , ebr and ebg pins instead of the reset , br and bg pins. the bg output is three-stated. these signals do not need to be jumper-isolated in your system. the ez-ice connects to your target system via a ribbon cable and a 14-pin female plug. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 8. you must add this connector to your target board design if you intend to use the ez-ice. be sure to allow enough room in your system to fit the ez-ice probe onto the 14-pin connector.
adsp-2184 C12C rev. 0 12 34 56 78 910 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset figure 8. target board connector for ez-ice the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tionyou must remove pin 7 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spac- ing should be 0.1 0.1 inches. the pin strip header must have at least 0.15-inch clearance on all sides to accept the ez-ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie and samtec. target memory interface for your target system to be compatible with the ez-ice emu- lator, it must comply with the memory interface guidelines listed below. pm, dm, bm, iom, and cm design a program memory (pm), data memory (dm), byte memory (bm), i/o memory (iom) and composite memory (cm) external interfaces to comply with worst case device tim- ing requirements and switching characteristics as specified in this dsps data sheet. the performance of the ez-ice may ap- proach published worst case specifications for some memory access timing requirements and switching characteristics. note: if your target does not meet the worst case chip specifica- tions for memory access parameters, you may not be able to emulate your circuitry at the desired clkin frequency. depend- ing on the severity of the specification violation, you may have trouble manufacturing your system as dsp components statisti- cally vary in switching characteristics and timing requirements within published limits. restriction: all memory strobe signals on the adsp-2184 ( rd , wr , pms , dms , bms , cms and ioms ) used in your target system must have 10 k w pull-up resistors connected when the ez-ice is being used. the pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical ez-ice debugging sessions. these resistors may be removed at your option when the ez-ice is not being used. target system interface signals when the ez-ice board is installed, the performance on some system signals change. design your system to be compatible with the following system interface signal changes introduced by the ez-ice board: ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the reset signal. ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the br signal. ? ez-ice emulation ignores reset and br when single- stepping. ? ez-ice emulation ignores reset and br when in emulator space (dsp halted). ? ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the dsps external memory bus only if bus grant ( bg ) is asserted by the ez-ice boards dsp.
C13C adsp-2184 rev. 0 recommended operating conditions b grade parameter min max unit v dd 4.5 5.5 v t amb C40 +85 c electrical characteristics b grade parameter test conditions min typ max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 m a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max v in = 0 v 10 m a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 8 10 m a i ozl three-state leakage current 7 @ v dd = max v in = 0 v 8 , t ck = 25 ns 10 m a i dd supply current (idle) 9 @ v dd = 5.0 14 ma i dd supply current (dynamic) 10, 11 @ v dd = 5.0 t amb = +25 c t ck = 25 ns 60 ma c i input pin capacitance 3, 6, 12 @ v in = 2.5 v, f in = 1.0 mhz, 8 pf t amb = +25 c c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c8pf notes 1 bidirectional pins: d0Cd23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1Ca13, pf0Cpf7. 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd . 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2-0, bgh . 5 although specified for ttl outputs, all adsp-2184 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0Ca13, d0Cd23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rsf1, pf0Cpf7. 8 0 v on br . 9 idle refers to adsp-2184 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 12 applies to lqfp package type. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. specifications
adsp-2184 C14C rev. 0 esd sensitivity esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-2184 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) lqfp . . . . . . . . . . . . . . . . +280 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing parameters general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the proces- sor operates correctly with other devices. memory timing specifications the table below shows common memory device specifications and the corresponding adsp-2184 timing parameters, for your convenience. memory adsp-2184 timing device timing parameter specification parameter definition address setup to t asw a0Ca13, xms setup write start before wr low address setup to t aw a0Ca13, xms setup write end before wr deasserted address hold time t wra a0Ca13, xms hold before wr low data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0Ca13, xms to data valid xms = pms, dms, bms, cms, ioms. frequency dependency for timing specifications t ck is defined as 0.5 t cki . the adsp-2184 uses an input clock with a frequency equal to half the instruction rate: a 20 mhz input clock (which is equivalent to 50 ns) yields a 25 ns proces- sor cycle (equivalent to 40 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing para- meters to obtain the specification value. example: t ckh = 0.5 t ck C 7 ns = 0.5 (25 ns) C 7 ns = 5.5 ns warning! esd sensitive device
adsp-2184 C15C rev. 0 timing parameters parameter min max unit clock signals and reset timing requirements : t cki clkin period 50 150 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristics: t ckl clkout width low 0.5 t ck C 7 ns t ckh clkout width high 0.5 t ck C 7 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirements : t rsp reset width low 1 5 t ck ns t ms mode setup before reset high 2 ns t mh mode setup after reset high 5 ns notes 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable clkin (not including crystal oscillator start-up time). t ckoh t cki t ckih t ckil t ckh t ckl t mh t ms clkin clkout pf(2:0) * reset * pf2 is mode c, pf1 is mode b, pf0 is mode a figure 9. clock signals
adsp-2184 C16C rev. 0 timing parameters parameter min max unit interrupts and flag timing requirements : t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25 t ck + 15 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25 t ck ns switching characteristics : t foh flag output hold after clkout low 5 0.25 t ck C 7 ns t fod flag output delay from clkout low 5 0.5 t ck + 6 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on t he following cycle. (refer to interrupt controller operation in the program control chapter of the adsp-2100 family users manual , third edition , for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , irql0 , irql1 , irqe . 4 pfx = pf0, pf1, pf2, pf3, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, fl0, fl1, fl2, flag_out. t fod t foh t ifh t ifs clkout flag outputs irq x fi pfx figure 10. interrupts and flags
adsp-2184 C17C rev. 0 parameter min max unit bus requestCbus grant timing requirements : t bh br hold after clkout high 1 0.25 t ck + 2 ns t bs br setup before clkout low 1 0.25 t ck + 17 ns switching characteristics : t sd clkout high to xms , rd , wr disable 0.25 t ck + 10 ns t sdb xms , rd , wr disable to bg low 0 ns t se bg high to xms , rd , wr enable 0 ns t sec xms , rd , wr enable to clkout high 0.25 t ck C 7 ns t sdbh xms , rd , wr disable to bgh low 2 0ns t seh bgh high to xms , rd , wr enable 2 0ns notes xms = pms , dms , cms , ioms , bms . 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recogniz ed on the following cycle. refer to the adsp-2100 family users manual , third edition , for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor requires control of the bus to continue. clkout t sd t sdb t se t sec t sdbh t seh t bs br t bh clkout pms, dms bms, rd wr bg bgh figure 11. bus requestCbus grant
adsp-2184 C18C rev. 0 timing parameters parameter min max unit memory read timing requirements : t rdd rd low to data valid 0.5 t ck C 9 + w ns t aa a0Ca13, xms to data valid 0.75 t ck C 12.5 + w ns t rdh data hold from rd high 1 ns switching characteristics : t rp rd pulsewidth 0.5 t ck C 5 + w ns t crd clkout high to rd low 0.25 t ck C 5 0.25 t ck + 7 ns t asr a0Ca13, xms setup before rd low 0.25 t ck C 6 ns t rda a0Ca13, xms hold after rd deasserted 0.25 t ck C 3 ns t rwr rd high to rd or wr low 0.5 t ck C 5 ns w = wait states t ck . xms = pms , dms , cms , ioms , bms . clkout a0 C a13 d t rda t rwr t rp t asr t crd t rdd t aa t rdh dms, pms, bms, ioms, cms rd wr figure 12. memory read
adsp-2184 C19C rev. 0 parameter min max unit memory write switching characteristics : t dw data setup before wr high 0.5 t ck C 7+ w ns t dh data hold after wr high 0.25 t ck C 2 ns t wp wr pulsewidth 0.5 t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a0Ca13, xms setup before wr low 0.25 t ck C 6 ns t ddr data disable before wr or rd low 0.25 t ck C 7 ns t cwr clkout high to wr low 0.25 t ck C 5 0.25 t ck + 7 ns t aw a0Ca13, xms , setup before wr deasserted 0.75 t ck C 9 + w ns t wra a0Ca13, xms hold after wr deasserted 0.25 t ck C 3 ns t wwr wr high to rd or wr low 0.5 t ck C 5 ns w = wait states t ck . xms = pms , dms , cms , ioms , bms . clkout a0Ca13 d t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr dms, pms, bms, cms, ioms rd wr figure 13. memory write
adsp-2184 C20C rev. 0 timing parameters parameter min max unit serial ports timing requirements : t sck sclk period 50 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 8 ns t scp sclk in width 20 ns switching characteristics : t cc clkout high to sclk out 0.25 t ck 0.25 t ck + 10 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 15 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 15 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 14 ns t scdd sclk high to dt disable 15 ns t rdv rfs (multichannel, frame delay zero) to dt valid 15 ns clkout sclk tfs out rfs out dt alternate frame mode t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv multichannel mode, frame delay 0 (mfd = 0) dr tfs in rfs in rfs out tfs out t tdv t scdv t rd t scp t sck t scp tfs in rfs in alternate frame mode t rdv multichannel mode, frame delay 0 (mfd = 0) t tdv t tde figure 14. serial ports
adsp-2184 C21C rev. 0 parameter min max unit idma address latch timing requirements : t ialp duration of address latch 1, 2 10 ns t iasu iad15C0 address setup before address latch end 2 5ns t iah iad15C0 address hold after address latch end 2 3ns t ika iack low before start of address latch 2, 3 0ns t ials start of write or read after address latch end 2, 3 3ns notes 1 start of address latch = is low and ial high. 2 end of address latch = is high or ial low. 3 start of write or read = is low and iwr low or ird low. t ika iad 15C0 iack ial is ird iwr or t ialp t iasu t iah t ials figure 15. idma address latch
adsp-2184 C22C rev. 0 timing parameters parameter min max unit idma write, short write cycle timing requirements : t ikw iack low before start of write 1 0ns t iwp duration of write 1, 2 15 ns t idsu iad15C0 data setup before end of write 2, 3, 4 5ns t idh iad15C0 data hold after end of write 2, 3, 4 2ns switching characteristic : t ikhw start of write to iack high 15 ns notes 1 start of write = is low and iwr low. 2 end of write = is high or iwr high. 3 if write pulse ends before iack low, use specifications t idsu , t idh . 4 if write pulse ends after iack low, use specifications t iksu , t ikh . iad 15C0 data t ikhw t ikw t idsu iack t iwp t idh is iwr figure 16. idma write, short write cycle
adsp-2184 C23C rev. 0 parameter min max unit idma write, long write cycle timing requirements : t ikw iack low before start of write 1 0ns t iksu iad15C0 data setup before iack low 2, 3, 4 0.5 t ck + 10 ns t ikh iad15C0 data hold after iack low 2, 3, 4 2ns switching characteristics : t iklw start of write to iack low 4 1.5 t ck ns t ikhw start of write to iack high 15 ns notes 1 start of write = is low and iwr low. 2 if write pulse ends before iack low, use specifications t idsu , t idh . 3 if write pulse ends after iack low, use specifications t iksu , t ikh . 4 this is the earliest time for iack low from start of write. for idma write cycle relationships, please refer to the adsp-2100 family users manual , third edition . iad 15C0 data t ikhw t ikw iack is iwr t iklw t ikh t iksu figure 17. idma write, long write cycle
adsp-2184 C24C rev. 0 timing parameters parameter min max unit idma read, long read cycle timing requirements : t ikr iack low before start of read 1 0ns t irk end of read after iack low 2 ns switching characteristics : t ikhr iack high after start of read 1 15 ns t ikds iad15C0 data setup before iack low 0.5 t ck C 10 ns t ikdh iad15C0 data hold after end of read 2 0ns t ikdd iad15C0 data disabled after end of read 2 10 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 15 ns t irdh1 iad15C0 previous data hold after start of read (dm/pm1) 3 2 t ck C 5 ns t irdh2 iad15C0 previous data hold after start of read (pm2) 4 t ck C 5 ns notes 1 start of read = is low and ird low. 2 end of read = is high or ird high. 3 dm read or first half of pm read. 4 second half of pm read. t irk t ikr previous data read data t ikhr t ikds t irdv t irdh t ikdd t irde t ikdh iad 15C0 iack is ird figure 18. idma read, long read cycle
adsp-2184 C25C rev. 0 parameter min max unit idma read, short read cycle timing requirements : t ikr iack low before start of read 1 0ns t irp duration of read 15 ns switching characteristics : t ikhr iack high after start of read 1 15 ns t ikdh iad15C0 data hold after end of read 2 0ns t ikdd iad15C0 data disabled after end of read 2 10 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 15 ns notes 1 start of read = is low and ird low. 2 end of read = is high or ird high. t irp t ikr previous data t ikhr t irdv t ikdd t irde t ikdh iad 15C0 iack is ird figure 19. idma read, short read cycle
adsp-2184 C26C rev. 0 output drive currents figure 20 shows typical i-v characteristics for the output drivers of the adsp -2184. the curves represent the current drive capability of the output drivers as a function of output voltage. source voltage C v 0 60 10 20 30 40 50 source current C ma 60 0 C20 C40 C60 40 20 v dd = 5.0v @ +25 8 c v dd = 5.5v @ C40 8 c v dd = 4.5v @ +85 8 c v dd = 5.0v @ +25 8 c v dd = 4.5v @ +85 8 c v dd = 5.5v @ C40 8 c v ol v oh figure 20. typical drive currents power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 25 ns. total power dissipation = p int + ( c v dd 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 21). ( c v dd 2 f ) is calculated for each output: # of pins 3 c 3 v dd 2 3 f address, dms 8 10 pf 5 2 v 40 mhz = 80 mw data output, wr 9 10 pf 5 2 v 20 mhz = 45 mw rd 1 10 pf 5 2 v 20 mhz = 5 mw clkout 1 10 pf 5 2 v 40 mhz = 10 mw 140 mw total power dissipation for this example is pint + 40 mw. valid for all temperature grades. 1 power reflects device operating with no output loads. 2 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14) 30% are type 2 and type 6, and 20% are idle instructions. 3 idle refers to adsp-2184 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 4 typical power dissipation at 5.0v v dd and t a = 25 8 c except where specified. 65 25 40 35 30 60 55 45 50 power (p idle n ) C mw 62.1mw 34.7mw 32.8mw 34.3mw 36.6mw 70.55mw idle (16) idle (128) idle power, idle n modes 2 70 75 40 95 70 65 60 55 90 85 75 80 50 power (p idle ) C mw 82.28mw 91.52mw v dd = 5.5v 62.1mw 70.55mw v dd = 5.0v 44.73mw 51.705mw v dd = 4.5v power, idle 1, 2, 4 1/t cyc C mhz 33.33 40 175 400 275 250 225 200 375 350 300 325 330mw 250mw 180mw 300mw 225mw 2184 power, internal 1, 2, 3 385mw power (p int ) C mw v dd = 5.5v v dd = 5.0v v dd = 4.5v 45 1/t cyc C mhz 33.33 40 1/t cyc C mhz 33.33 40 150 figure 21. power vs. frequency
adsp-2184 C27C rev. 0 capacitive loading figures 22 and 23 show the capacitive loading characteristics of the adsp-2184. c l C pf rise time (0.4vC2.4v) C ns 30 300 0 50 100 150 200 250 25 15 10 5 0 20 t = +85 8 c v dd = 4.5v figure 22. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) c l C pf 14 0 valid output delay or hold C ns 50 100 150 250 200 12 4 2 C2 10 8 nominal 16 18 6 C4 C6 figure 23. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the out- put disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approximated by the fol- lowing equation: t decay = c l 0.5 v i l from which t dis = t measured C t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. 1.5v input or output 1.5v figure 24. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when that have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) C 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 25. output enable/disable to output pin 50pf +1.5v i oh i ol figure 26. equivalent device loading for ac measure- ments (including all fixtures)
adsp-2184 C28C rev. 0 environmental conditions ambient temperature rating: t amb =t case C (pd 3 q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package u ja u jc u ca lqfp 50 c/w 2 c/w 48 c/w 0 temperature C 8 c 10 idd C m a 1 100 1k 10k 20 60 80 100 120 40 5.6v 5.0v figure 27. power-down supply current
adsp-2184 C29C rev. 0 100-lead lqfp package pinout 5 4 3 2 7 6 9 8 1 d19 d18 d17 d16 irqe +pf4 irql0 +pf5 gnd irql1 +pf6 dt0 tfs0 sclk0 vdd dt1 tfs1 rfs1 dr1 gnd sclk1 ereset reset d15 d14 d13 d12 gnd d11 d10 d9 vdd gnd d8 d7/ iwr d6/ ird d5/ial d4/ is gnd vdd d3/ iack d2/iad15 d1/iad14 d0/iad13 bg ebg br ebr a4/iad3 a5/iad4 gnd a6/iad5 a7/iad6 a8/iad7 a9/iad8 a10/iad9 a11/iad10 a12/iad11 a13/iad12 gnd clkin xtal vdd clkout gnd vdd wr rd bms dms pms ioms cms 71 72 73 74 69 70 67 68 65 66 75 60 61 62 63 58 59 56 57 54 55 64 52 53 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 identifier top view (not to scale) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 adsp-2184 irq2 +pf7 rfs0 dr0 ems ee elout eclk elin eint a3/iad2 a2/iad1 a1/iad0 a0 pwdack bgh fl0 fl1 fl2 d23 d22 d21 d20 gnd pf1 [mode b] gnd pwd vdd pf0 [mode a] pf2 [mode c] pf3
adsp-2184 C30C rev. 0 lqfp pin configurations lqfp pin lqfp pin lqfp pin lqfp pin number name number name number name number name 1 a4/ iad3 26 irqe + pf4 51 ebr 76 d16 2 a5/ iad4 27 irql0 + pf5 52 br 77 d17 3gnd28gnd53 ebg 78 d18 4 a6/ iad5 29 irql1 + pf6 54 bg 79 d19 5 a7/ iad6 30 irq2 + pf7 55 d0/ iad13 80 gnd 6 a8/ iad7 31 dt0 56 d1/ iad14 81 d20 7 a9/ iad8 32 tfs0 57 d2/ iad15 82 d21 8 a10/ iad9 33 rfs0 58 d3/ iack 83 d22 9 a11/ iad10 34 dr0 59 vdd 84 d23 10 a12/ iad11 35 sclk0 60 gnd 85 fl2 11 a13/ iad12 36 vdd 61 d4/ is 86 fl1 12 gnd 37 dt1 62 d5/ ial 87 fl0 13 clkin 38 tfs1 63 d6/ ird 88 pf3 14 xtal 39 rfs1 64 d7/ iwr 89 pf2 [mode c] 15 vdd 40 dr1 65 d8 90 vdd 16 clkout 41 gnd 66 gnd 91 pwd 17 gnd 42 sclk1 67 vdd 92 gnd 18 vdd 43 ereset 68 d9 93 pf1 [mode b] 19 wr 44 reset 69 d10 94 pf0 [mode a] 20 rd 45 ems 70 d11 95 bgh 21 bms 46 ee 71 gnd 96 pwdack 22 dms 47 eclk 72 d12 97 a0 23 pms 48 elout 73 d13 98 a1/ iad0 24 ioms 49 elin 74 d14 99 a2/ iad1 25 cms 50 eint 75 d15 100 a3/ iad2 the adsp-2184 package pinout is shown in the table below. pin names in bold text replace the plain text named functions when mode c = 1. a + sign separates two functions when either function can be active for either major i/o mode. signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of reset .
adsp-2184 C31C rev. 0 100-lead metric thin plastic quad flatpack (lqfp) (st-100) seating plane 0.030 (0.75) 0.024 (0.60) typ 0.020 (0.50) 0.063 (1.60) max 12 8 typ 0.007 (0.177) 0.005 (0.127) typ 0.003 (0.077) 6 8 4 8 0 8 C 7 8 0.004 (0.102) max lead coplanarity top view (pins down) 1 25 26 51 50 75 100 76 0.011 (0.27) 0.009 (0.22) typ 0.007 (0.17) 0.640 (16.25) 0.630 (16.00) typ sq 0.620 (15.75) 0.020 (0.50) bsc lead pitch 0.553 (14.05) 0.551 (14.00) typ sq 0.549 (13.95) 0.472 (12.00) bsc lead width note: the actual position of each lead is within (0.08) 0.0032 from its ideal position when measured in the lateral direction. center figures are typical unless otherwise noted ordering guide ambient instruction temperature rate package package part number range (mhz) description option* adsp-2184bst-160 C40 c to +85 c 40.0 100-lead lqfp st-100 *st = plastic thin quad flatpack (lqfp). outline dimensions dimensions shown in inches and (mm). c3418C2C5/99 printed in u.s.a.

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